Fixes/Enhancements
- Added address decode support for AMD Rembrandt/Zen 3+ (Family 19, Model 40-4F) chipsets
- Fixed module/chip decoding for SODIMM/CSODIMM modules on Intel Arrow Lake chipsets
- Fixed DDR5 SODIMMs incorrectly identified as UDIMMs in DIMM results screen
- Fixed module decoding for 2-slot Intel Arrow Lake boards
- Fixed bug in obtaining SMBIOS memory info for 2-slot Intel Arrow Lake boards
- Improved execution time of cache/memory benchmark tests by adjusting number of iterations based on capacity
- Improved execution time of rdtsc clock speed measurement
- Reduced significant delays prior to starting memory tests due to initializing and reading of memory controller registers
- Fixed incorrect measurement of cache/memory speeds for ARM64 chipsets
- Applied workaround for enabling performance timers (CNTP_CTL_EL0) when running in a lower exception level for ARM64 chipsets
- Removed validity checks causing failure to obtain DDR4 DIMM temperature data
- Fixed bug in enabling ECC injection for Intel Arrow Lake/Lunar Lake chipsets
- Fixed incorrect memory clock speed reported for Intel Ivy Bridge chipsets
- Updated JEDEC manufacturer ID codes based on JEP106BL (Feb 2025)
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